Update on the Data Acquisition System development in the UK.ppt

UpdateontheDataAcquisitionSystemdevelopmentintheUKValeriaBartsch,onbehalfofCALICE-UKCollaborationDAQarchitectureDetectorUnit:Sensors&ASICsDIF:DetectorInterFace-connectsgenericDAQandservicesLDA:Link/DataAggregator–fanout/inDIFs&drivelinktoODRODR:OffDetectorReceiver–&C:Clock&Control:FanouttoODRs(orLDAs)LDALDAHostPCPCIeODRHostPCPCIeODRDetectorUnitDIFC&CDetectorUnitDIFDetectorUnitDIFDetectorUnitDIFStorage1-3GbFibre50-150MbpsHDMIcabling10--1mDetectorCountingRoomDAQarchitectureLDALDAHostPCPCIeODRHostPCPCIeODRDetectorUnitDIFC&CDetectorUnitDIFDetectorUnitDIFDetectorUnitDIFStorage1-3GbFibre50-150MbpsHDMIcabling10--1mDetectorCountingRoomOffDetectorReceiver(ODR)Hardware:mercialFPGAdev-board:PLDAXPressFX100XilinxVirtex4,8xPCIe,2xSFP(3morewithexpansionboard)SFPsforopticlinkExpansion()ReceivesmoduledatafromLDAPCI-Expresscard,-4links/card(ormore),1-2cards/PCBuffersandtransferstostoreasfastaspossibleSendscontrolsandconfigtoLDAfordistributiontoDIFsPerformancestudies&optimisationon-.,A.******@RHULODR-essratetransferofthedatafromODRmemorytotheuser-programmemory=>220-320MByte/.,A.******@RHULLinkDataAggregator(LDA)Hardware:PCBsdesignedandgetcustomizedin1weektimebyEnterpointCarrierBD2boardlikelytobeconstrainedtoatleastaSpartan32000modelGigabitlinksasshownbelow,.,ManchesterLinkDataAggregator(LDA)Firmware:,.,oanexternalclockandaninternalclockfortestinganddebuggingprovidesinputlinesforcontrolsandfasttriggerboardtobebuiltatRALdesignfinalised