A Clock Distribution Technique with an Automatic pensation Circuit：一种自动倾斜补偿电路的时钟分配技术.pdf

Institute of Electronics, Information, munication Engineers NII-Electronic Library Service Institute Information, CommunicationEngineers IEICETRANS, ELECTRON.. N,Ol..ESI-C, lg9S 277 PAPER 1 ACIock Distribution pensationCircuit withanAutomaticSkew HirokiSuToHta)and KimihiroYAMAKOSHV, Members SUMMARY Thls paperdescribes alo".skew clockdistribu- multiple alltomatic ske"'campen- sation circu] the Teund-trip dela}, through pair of matched rionlines and corrects thedelay ofthe varj- ab]edelaylines, maintains ske-' and dela}rfrom among mu]tipie targetsbelow the time of the delay lines any manual adjustment. Measured results show thattheinitial clock ske"' ot'900ps isautomarica]ly reduced to 30ps ataclockfrcquency ofupto150MHz with60ps ofc[ock jilter, Moreoyer. they show thattheinitial clockdelay ofl5oops is cancelled 60ps de[ay canbe achicved. Thepower dissipation i$100 at2jOMHz, kev ske"; cloekdistrihuiion, compensation. variable delaJ, line,CMOS High-density,high-speed, and low-powerLSIs are the key elements plex monolithic systems. With the recentadvances infabrication anddesign technology, theoperating speed ofCMOS LSIshasbeen steadi]y increasing andit has already reached afewhundTed MHz[1],[2].Thishas enabled the eonstruction of higher-puters forinstance. In synehronous digital systems, one ofthe bigprob- lenis