Lec06(第六节).ppt

1 Digital Logic Design and Application Jin Yanhua Lecture #6 CMOS Dynamic Electrical Behavior Other CMOS Input and Output Structures UESTC, Spring 2012 Jin. UESTC 2 Digital Logic Design and Application 答疑安排?答疑地点: A教2楼教师休息室电梯/(A202) 旁边?答疑时间: 周二中午 1 : 00-2 : 00 周二 7、8节周四 3、4节周五 3、4节高性价比手机选购. UESTC 3 Digital Logic Design and Application Last Time CMOS Steady-State Electrical Behavior ? Logic Levels and Noise Margins 30% ? HIGH ABNOMAL LOW V OLmax V ILmax V IHmin V OHmin High-state DC noise margin Low-state DC noise margin ? GND+ 30% 70% Jin. UESTC 4 Digital Logic Design and Application Last Time ? Circuit Behavior with Resistive Loads ? The load is specified in terms of current. 例: P177 The load make the output voltage deteriorate. Ensure the sourcing and sinking current within specifications. = + R Thev V Thev + Jin. UESTC 5 Digital Logic Design and Application Last Time ? Circuit Behavior with Nonideal Inputs i DV IN12V DD V OUTV IN 电压传输特性电流传输特性 The output voltage away from the power-supply rail. Output current ?, Power Consumption ? Current Spikes Jin. UESTC 6 Digital Logic Design and Application Last Time ? Fanout ? The sum of the I IL(I IH ) values of the driven inputs may not exceed I OLmax (I OHmax ) of the driving output ? Need to do Thevenin-equivalent calculation for non- gate loads (LEDs, termination resistors, etc.) ? Effects of Loading ? Unused Inputs ? Never be left unconnected Jin. UESTC 7 Digital Logic Design and Application CMOS Dynamic Electrical Behavior ? Both the speed and the power consumption of a CMOS device depend to a large extent on dynamic characteristics of the device and its load. ? Speed depends on two characteristics: ? Transition Time (转换时间) ? Propagation Delay (传播延迟)≡ time that output takes to change states ≡ time from input changing to output changing Jin. UESTC 8 Digital Logic Design and Application Transition Time Depend on two f