H264_decoder on CellBE.ppt

1 A Scalable Parallel Decoder on the Cell Broadband Engine Architecture Michael A. Baker, Pravin Dalale , Karam S. Chatha , Sarma B. K. Vrudhula Arizona State University CODES+ISSS (The International Conference on Hardware-Software Codesign and System Synthesis) 2009 2 Outline ? Introduction and Motivation ? Opportunities for Parallelization in ? Implementation ? Performance Optimizations ? Experimental Results ? Conclusion 3 Motivation ? Multicore Architectures ? Scalability: more cores = more performance ? ? Standard for video applications including High Definition(HD ) ? Computationally expensive ? Cell Broadband Engine(CBE ) ? Common and inexpensive thanks to PS3 ? Low power high performance design gives a glimpse of future embedded architectures 4 IBM Cell Broadband Engine Architecture ? GHz ? 9 cores, 10 threads ?>200 Gflops(single precision) ?>20 Gflops(double precision) ? Up to 25 GB/s memory bandwidth ? Up to 75 GB/s I/O bandwidth ?>300 GB/s interconnect bus ./comm/. SPE: Synergistic Processor Element SPU: Synergistic Processor Unit SXU: SPU Core LS: Local Storage SMF: Synergistic Memory Flow Control EIB: Element Interconnect Bus PPE: PowerPC Processor Element PPU: PowerPC processor Unit PXU: Power Processor Unit MIC: Memory Interface Controller BIC: Bus Interface Controller L1: Memory Cache Internal to the CPU L2: Memory Cache External to the CPU 5 Advanced Video Coding ? is a pression standard ? Version pleted May 2003 ? ITU-T Video Coding Experts Group () ? ISO/IEC Moving Picture Experts Group (MPEG-4 AVC) ? Macroblock(MB ) based CODEC closely related to MPEG-2 ? Growing demand for HD and Wireless video ? 50% bit rate reduction over previous standard ? plexity approximately x MPEG2 6 : Decoder 7 Reference Code: FFmpeg ( Decoder) ? Open source video and audio converter ? Handles a multitude of formats ? Codecs o