基于DSP和FPGA的图像处理系统设计.doc

I 题目:基于 DSP 和 FPGA 的图像处理系统设计外文题目: IMAGE PROCESSING SYSTEM DESIGN BASED ON DSP AND FPGA 摘要本文研究了以 TI 高性能 DSP 为核心处理器的视频实时图像处理系统的设计原理与组成,并基于 DSP + FPGA 架构实现了视频图像处理系统。本图像处理系统主要由图像采集电路、图像处理电路、显示电路以及系统软件组成。 D 图像传感器采集复合视频信号,经过视频 A/D处理器( SAA7115 )转换成8 bit 的数字信号,通过 DMA 方式存放在双口 RAM 中,该处理器同时还输出像素时钟信号( PCLK ),场同步( CS )、行同步( HS )、奇偶场( OE )、复合消隐信号( BLANK )。数字信号处理器 DSP ( TMS320VC5501 ) 是本处理器的核心部分,其功能是完成整个系统的图像预处理以及数据流存储时序控制等功能。经过 DSP 处理后输出 8 bit 的数字视频信号以及像素时钟信号( PCLK )、场同步( CS )、行同步( HS ),一起送 FPGA 产生视频信号的时序逻辑,然后送视频 D/A处理器( SAA7105H ),最后通过 VGA 视频接口输出。静态双口 RAM 用于存储图像数据的, 图像数据的读写控制时序通过 DSP 来实现。视频 D/A 处理器( SAA7105H )将 FPGA 输出的数字视频信号、像素时钟、行场同步信号合成为彩色全电视信号然后通过 VGA 输出。该视频图像处理系统可以实现实时的数据视频信号的采集、处理及显示,可以应用于视频处理的相关领域。关键字: DSP ; FPGA ;图像处理;电路设计;系统软件 II Abstract This paper studies the system design principle position the of TI high performance DSP core processor for real-time video image processing , and it can achieve video image processing system based on the architecture of DSP and FPGA. The image processing system posed of image acquisition circuit, image processing circuit, display circuit and system software. After the D image sensor collect posite video signal, the video A/D processor (SAA7115) is converted into a digital signal of8 bit, which is stored in dual-port RAM through DMA, the processor also outputs pixel clock signal (PCLK), field synchronization ( CS ), synchronous (HS), parity field (OE), composite blanking signal (BLANK). DSP digital signal processor (TMS320VC5501) is the core part of this processor, its function is plete the whole system of image preprocessing and the sequence of data storage control . After DSP treatment, the output of the 8 bit digital video signal and a pixel clock signal (PCLK). The field synchronization (CS), synchronous (HS), which is send to FPGA for producing video signals, then transmitted to the video processor D/A (SAA7105), the final output through a VGA video. Static double port RAM is used to store the image data, the timing control of image