基于fpga的异步fifo的研究和设计.doc

基于FPGA的异步FIFO的研究和设计
摘要:为了使异步FIFO正确稳定的工作,同时最大限度的降低资源占有率,针对设计异步FIFO的难点分析了异步FIFO的结构和工作原理,提出了一种切实可行的设计方法。通过设计两个计数器分别对空、满标志位信号进行控制,确保了数据的正确写入与读出。采用了格雷码的方式最大限度降低了电路中亚稳态出现的概率,加强了整个系统的可靠性和抗干扰能力。结果表明该设计能够使数据稳定地写入和读出,实现了不同时钟域之间数据的无损传输同时资源利用率较高,具有很高的实用价值。
关键词:异步FIFO 亚稳态格雷码 FPGA
Research and Design of Asynchronous FIFO Base on FPGA
Cheng Guang-wei1, Liu Da-wei2
Department of Electronics Information Engineering,Xi’an Technological University
2. Department of Electronics Information Engineering,Xi’an Technological University)
Abstract:A practical design technique is proposed,In order to make the asynchronous FIFO stable work ,At the same time,maximum limit reduces the resource sharet. Through the analysis of the structure and operational principle of asynchronous FIFO,for meeting the difficult point of asynchronous FIFO. Ensuring writing in or reading out data without error by way of designing two counter to controll full and empty signals. Using the method of gray mode reduces the incidence of metastable state maximum,Strengthening the system reliability and anti jamming ability. The result shows that the design can make data write in or read out steady,realizing the aim of transmitting data without loss and have a high resource utilization rate,has very high practical value.
Keywords:Asynchronous FIFO Gray code Metastable state FPGA

随着用户需求的不断提高,在现代集成电路芯片设计中一个系统往往包含多个时钟,与此同时多