FPGA实验报告.doc

FPGA实验上机报告

实验二
Part1代码
LIBRARY ieee;
USE ;
ENTITY part1 IS
PORT(SW :IN STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDR :OUT STD_LOGIC_VECTOR(17 DOWNTO 0));
END part1;
ARCHITECTURE Behavior OF part1 IS
BEGIN
LEDR<=SW;
END Behavior;
运行结果:拨码开关控制LED闪亮
Nice 代码
LIBRARY ieee;
USE ;
ENTITY nice IS
PORT(SW :IN STD_LOGIC_VECTOR(0 TO 17);
HEX0 :OUT STD_LOGIC_VECTOR(0 TO 6);
LEDR :OUT STD_LOGIC_VECTOR(0 TO 17));
END nice;
ARCHITECTURE Behavior OF nice IS
SIGNAL temp :STD_LOGIC_VECTOR(0 TO 3);
BEGIN
LEDR<=SW;
temp(3)<=SW(0);
temp(2)<=SW(1);
temp(1)<=SW(2);
temp(0)<=SW(3);
PROCESS(temp)
BEGIN

CASE temp IS
WHEN "0000"=>HEX0<="1001111";
WHEN "0001"=>HEX0<="0010010";
WHEN "0010"=>HEX0<="0000110";
WHEN "0011"=>HEX0<="1101100";
WHEN "0100"=>HEX0<="1001100";
WHEN "0101"=>HEX0<="0100100";
WHEN "0110"=>HEX0<="0100000";
WHEN "0111"=>HEX0<="0001111";
WHEN "1000"=>HEX0<="0000000";
WHEN "1001"=>HEX0<="0000100";
WHEN OTHERS=>HEX0<="1001000";
END CASE;
END PROCESS;
END Behavior;
运行结果:拨码开关控制数码管显示数字

(1):
LIBRARY IEEE;
USE ;
USE ;
-----This is a simple watch with sec/min/hour display in DE2 broad
-----SW(0) is the reset input, when SW(0)=1,the program runs.
ENTITY watch IS
PORT(SW: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
clk_50:IN STD_LOGIC;
HEX0:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX2:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX3:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX4:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX5:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX6:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END watch;
--------------------------------------------------
ARCHITECTURE rtl OF watch IS
COMPONENT sec_clk IS -----create a clk signal 1Hz frequency
PORT(clk_50 :IN STD_LOGIC;
clk_div1 :OUT STD_LOGIC);
PONENT;
COMPONENT count4 IS -----s