【专题技术】MultiCoreExpo-Sonics_3.09.pdf

4th Annual
Using Multichannel DRAM
Subsystems to Create Scalable
Architecture for Video SOCs
Alex Chao
March 18, 2009
4th Annual
Video SoCs: Growing Fast plexity
• Video SoCs face plexity and need much more memory
bandwidth
– More and more features
• Advanced trick mode, 2D/3D GFX, Security (DRM)
– HD is now the standard resolution
– Latest and greatest algorithms
• State of the art pression standards: , VC-1, AVS
• Image quality improvements: Multi-scaling, noise reduction, alpha
blending, multi-plane posing
• Features and performance place heavy burden on memory
subsystems
• Increasing software burden requires more platform stability across
architecture generations, product lines and product derivatives
Multichannel DRAM Subsystems for Video SOCs 2
4th Annual
Example of a Video SOC (current generation)
Basic software
stack Transport
OSD Video
MP @ L3 Demux back-end
decoder
Host
CPU INTERCONNECT
INTERCONNECT
INTERCONNECT
Memory
Subsystem
Peripherals
GB/s – 2 GB/s
Multichannel DRAM Subsystems for Video SOCs 3
4th Annual
Example of a Video SOC (next generation)
dual HD stream
decoding
Full software stack
HiP
***@ HiP 2D/3D Transport Display
@
decoder GFX Demux processing
decoder
Host CPU Audio DSP
INTERCONNECT
INTERCONNECT
Video out
INTERCONNECT Memory Memory
Subsystem Subsystem
#1 #2
Peripherals
8 GB/s – 11 GB/s
Multichannel DRAM Subsystems for Video SOCs 4
4th Annual
Concurrency in Video SoCs
Video SoCs process lots of data in parallel, municate…
Transport demux
Graphic Engines
Audio Decode
Decode
Video Out
Bitstream Entropy iScan Recon- Loop Decoded
Entropy iScan iTrans Recon- Loop
Decoding iQuant iTrans struction Filter Frames
Decoding iQuant struction Filter
Intra
Intra
Prediction
Prediction
MC
MC
Prediction
Prediction
Multichannel DRAM Subsystems for Video SOCs 5