高性能处理器存取关键技术设计与优化.docx

高性能处理器存取关键技术的设计与优化
摘要
随着半导体工艺和计算机体系结构的不断发展,高性能处理器的运行速度和存储器运行速度之间的差异变得愈加明显,成为制约处理器性能提升的因素之一。从指令执行的角度分析,解决存储墙问题就是提高存储指令的执行效率。论文以存取队列为研究突破口,对高性能处理器中的存取关键技术进行了研究和设计。
本论文对高性能处理器中的队列设计和主要的优化方法进行研究,在载入指令重新执行和“存储脆弱窗”算法的基础上,提出新的队列设计方案,称为 ESVW。新的设计充分利用载入和存储数据的局部性,进一步降低存储系统被访问的频率。基于相同的设计思路,论文将存取队列和分布式设计的思想引入阵列处理器设计,提出基于存取队列和分布式缓存的处理器架构,充分利用 DSP 阵列处理器中载入和存储数据的局部性,缓解非规则数据存取操作灵活性差的问题,使存储带宽不再成为性能提升的瓶颈。
论文完成 ESVW 的 RTL 设计和逻辑综合,并对性能、面积等参数进行分析。借助 SimpleScalar 仿真器和 SPEC 测试程序,证实 ESVW 可进一步降低指令访问存储系统的频率,相比于 SVW 使系统获得约 2%的性能提升。论文完成 DSP 阵列处理器中主要模块的 RTL 设计、验证和逻辑综合。使用二维离散余弦变换,快速傅里叶变换和 FIR 滤波等常见算法对存取队列的性能进行评估。结果显示,使用存取队列设计前后,系统获得约 5%的性能提升,芯片面积增加 %。
关键词:高性能处理器,存取队列,SVW 算法,分布式缓存
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DESIGN AND OPTIMIZATION OF KEY LOAD STORE TECHNOLOGY IN HIGH PERFORMANCE PROCESSORISSER
ABSTRACT
With semiconductor technology puter architecture developments, speed gap between high performance processor and memory system es even more obvious, constraining processor further development. From the perspective of instruction execution, to solve storage wall problem is to increase data load and store efficiency. Taking load and store queue as breakthrough, this paper conducts research and design on key data load and store technologies in high performance processor.
After studying load store queue and optimization methods in high performance processor, this paper introduces ESVW design scheme, based on load instruction re-execution and Store Vulnerability Window methods. ESVW makes full use of load and store data locality, further reduces memory access rate. Based on the same design methodology, this paper introduces queue and distribution into array processor design, suggests array processor architecture with load store queue and distributed cache, in order to take full advantage of load and store data locality, to mitigate low flexibility problem of irregular data access, and make memory bandwidth no longer performance bottleneck.
RTL design, verification and logic synthesis of ESVW are achieved, analysis