cmos电荷泵锁相环的设计及相位噪声的研究-微电子学与固体电子学专业毕业论文.docx

Design of a CMOS Charge--Pump PLL and Investigation of the Phase Noise
Abstract
With the development‘of the integrated circuit technology,the PLL(Phase Locked Loop)obtains more and more (Charge·Pump PLL) e the mainstream and play an important role in VLSI and SoC(System on Chip)because of the merit of smaller phase difference and bigger capture range.
This thesis designed a CPPLL which was based on CMOS technology and adopted top·down ,the VHDL-AMS behavioral modeling of the close—loop system was desi gned based on the fundamental of CPPLL and the characteristic of VHDL-AMS ,phase frequency detector,charge pump,loop filter,voltage controlled oscillator,divider and the clock distribution circuit were designed under the guidance of the behavioral model and the specification of the application noise and jitter were analysed and simulated on the ,the layout was designed and taped out.
The D/A converter including the CPPLL which was designed by this thesis has been fabricated in MPW based on the CMOS 2P3M technology and passed the preliminary actual PLL circuit supports frequency division of 4-32,
and outputs clock signals of different power supply is adj ustable frequency range is 96~ power dissipation is less than the noise iS less than 1 00dBc/Hz.
Keywords:charge-pump phase locked loop,VHDL-AMS,behavioral modeling, phase noise,j itter
插图清单
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图2—4锁相环能量谱 .8
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图2-6鉴相器的示意图 1 3
图2—7鉴频鉴相器框图及其状态转换 13
图2—8基本的电荷泵结构 ..14
图2-9三阶无源低通滤波器 ..15
0压控振荡器 。l 7
PLL行为模型的仿真 ..20
DAC系统结构图 22
“死区” 24
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图3—8电荷泵电路 28
图3-9滤波器 29
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1系统开环幅频特性 .33
2负反馈系统 ..34
3 N级环形振荡器 34
4六级环形振荡器 .35
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6整形电路 38