EDA常见实例源程序代码vhdl.doc

第4章用VHDL程序实现常用逻辑电路
组合逻辑电路设计
基本逻辑门
library ieee;
use ;
entity jbm is
port(a,b: in bit;
f1,f2,f3,f4,f5,f: out bit);
end jbm;
architecture a of jbm is
begin
f1<=a and b; --构成与门
f2<=a or b; --构成或门
f<=not a; --构成非门
f3<=a nand b; --构成与非门
f4<=a nor b; --构成异或门
f5<=not(a xor b); --构成异或非门即同门
end;
三态门
library ieee;
use ;
entity tri_s is
port(enable: in std_logic;
datain: in std_logic_vector(7 downto 0);
dataout: out std_logic_vector(7 downto0));
end tri_s;
architecture bhv of tri_s is
begin
process(enable,datain)
begin
if enable='1' then
dataout<=datain;
else
dataout<="ZZZZZZZZ";
end if;
end process;
end bhv;
3-8译码器
library ieee;
use ;
entity decoder3_8 is
port(a,b,c,g1,g2a,g2b: in std_logic;
y: out std_logic_vector(7 downto 0));
end decoder3_8;
architecture a of decoder3_8 is
signal dz:std_logic_vector(2 downto 0);
begin
dz<=c&b&a;
process (dz,g1,g2a,g2b)
begin
if(g1='1'and g2a='0'and g2b='0')then
case dz is
when "000"=> y<="11111110";
when "001"=> y<="11111101";
when "010"=> y<="11111011";
when "011"=> y<="11110111";
when "100"=> y<="11101111";
when "101"=> y<="11011111";
when "110"=> y<="10111111";
when "111"=> y<="01111111";
when others=>y<="XXXXXXXX";
end case;
else
y<="11111111";
end if;
end process;
优先编码器
library ieee;
use
entity coder is
port(din: in std_logic_vector(0 to 7);
output: out std_logic_vector(0 to 2));
end coder;
architecture behave of coder is
signal sint: std_logic_vevtor(4 downto 0);
begin
process(din)
begin
if (din(7)='0') then
output <= "000" ;
elsif (din(6)='0') then
output <= "100" ;
elsif (din(5)='0') then
output <= "010" ;
elsif (din(4)='0') then
output <= "110" ;
elsif (din(3)='0') then
output <= "001" ;
elsif (din(2)='0') then
output <= "101" ;
elsif (din(1)='0') then
output <