电子科技大学2015-2016 学年第二学期期末考试 A 卷 考试科目: 数字逻辑设计及应用考试形式: 闭卷考试日期: 2016 年 6 月 29 日 成绩构成比例:平时 30/20 %, 期中 30/20 %, 小班研讨 20 %, 期末 40 % 本试卷由 V 部分构成,共 5 页。考试时长: 120 分钟注: 题号 I II III IV V 合计 得分 得分
I. Please fill out the correct answers in the brackets “( )”. ( 4’ X 10 = 40’) 1. If a T flip flop with an enable input EN is constructed by a D flip flop, then the input D=( EN⊕Q ). 2. If the minimal output voltage increment of an 8-bit DAC is , then the output voltage is ( 77* 或 ) V, when the input is 01001101. 3. A 16Kx8 ROM, which can implement binational circuit with ( 14 ) inputs and ( 8 ) outputs at most, can be built by ( 4 ) 8Kx4 ROMs . 4. To design a "1101001110" serial sequence generator, ( 4 ) flip flops are need at least. 5. A 4-bit linear feedback shift-register (LFSR) counter with no modification can have ( 15 ) valid states. 6. To build a modulo -256 counter, it requires at least ( 8 ) flip flops. 7. A ( mealy ) state machine is a sequential circuit whose output depends on the state and inputs. 8. There are ( 2n-2n ) invalid states for an n-bit Johnson counter. 每个空格4分,错一个,扣4分。 得分 I I. Choose the correct answer and fill the item number in the brackets. (3’ X 5=15’) 1. According to the circuit as shown in , the output F is ( a ) a. b. c. d.