【EDA技术与VHDL课件】第13章 VHDL仿真.pdf

(Simulation),是对电路设计的一种间接的检测方法,是利用计算机对整个硬件系统进行模拟检测,但却可以不接触具体的硬件系统。较大规模的VHDL系统设计的最后完成必须经历多层次的仿真测试过程,其中将包括针对系统的VHDL行为仿真、分模块的时序仿真和硬件仿真,直至最后系统级的硬件仿真测试。(数据和波形)图13-【例13-1】LIBRARYIEEE;;ENTITYand1ISPORT(aaa,bbb:c:OUTSTD_LOGIC);ENDand1;<=aaaANDbbb;END;康芯科技【例13-2】XLIBRARYIEEE;;ENTITYTRIBUF_and1ISGENERIC(ttri:TIME:=1ns;ttxz:TIME:=1ns;ttzx:TIME:=1ns);PORT(in1:INstd_logic;oe:INstd_logic;y:OUTstd_logic);ENDTRIBUF_and1;ARCHITECTUREbehaviorOFTRIBUF_and1ISBEGINPROCESS(in1,oe)BEGINIFoe'EVENTTHENIFoe='0'THENy<=TRANSPORT'Z'AFTERttxz;ELSIFoe='1'THENy<=TRANSPORTin1AFTERttzx;ENDIF;ELSIFoe='1'THENy<=TRANSPORTin1AFTERttri;ELSIFoe='0'THENy<=TRANSPORT'Z'AFTERttxz;ENDIF;ENDPROCESS;ENDbehavior;LIBRARYIEEE;;;ENTITYand1ISPORT(aaa:INstd_logic;bbb:c:OUTstd_logic);ENDand1;ARCHITECTUREEPF10K10LC84_a3OFand1IS......ENDEPF10K10LC84_a3;【例13-3】LIBRARYIEEE;;ENTITYADDER4ISPORT(a,b:ININTEGERRANGE0TO15;c:OUTINTEGERRANGE0TO15);ENDADDER4;ARCHITECTUREoneOFADDER4ISBEGINc<=a+b;ENDone;【例13-4】ENTITYSIGGENISPORT(sig1:OUTINTEGERRANGE0TO15;sig2:OUTINTEGERRANGE0TO15);END;ARCHITECTURESimOFSIGGENISBEGINsig1<=10,5AFTER200ns,8AFTER400ns;sig2<=3,4AFTER100ns,6AFTER300ns;END;-【例13-5】ENTITYBENCHISEND;PONENTADDER4PORT(a,b:integerrange0to15;c:OUTINTEGERRANGE0TO15);PONENTSIGGENPORT(sig1:OUTINTEGERRANGE0TO15;sig2:OUTINTEGERRANGE0TO15);PONENT;SIGNALa,b,c:INTEGERRANGE0TO15;BEGINU1:ADDER4PORTMAP(a,b,c);U2:SIGGENPORTMAP(sig1=>a,sig2=>b);END;-3BENCH仿真波形图