’sbehavioralmodelingisnothigh-levelenoughPeoplegenerallyuseCorC++StandardMethodologyforICsSystem-leveldesignerswriteaCorC++modelWritteninastylized,hardware-likeformSometimesrefinedtobemorehardware-likeC/C++modelsimulatedtoverifyfunctionalityModelgiventoVerilog/VHDLcodersVerilogorVHDLspecificationwrittenModelssimulatedtogethertotestequivalenceVerilog/panyuseditsownsimulationlibrary“Throwthemodeloverthewall”approachmakesiteasytointroduceerrorsProblems:Systemdesignersdon’tknowVerilogorVHDLVerilogorVHDLcodersdon’andC++arebeingusedasad-hocmodelinglanguagesWhynotformalizetheiruse?WhynotinterpretthemashardwarespecificationlanguagesjustasVerilogandVHDLwere?SystemCdevelopedatmyformeremployerSynopsystodojustthisWhatIsSystemC?AsubsetofC++thatmodels/pilerthattranslatesthe“synthesissubset”listWhatIsSystemC?mercialproductSeeoreinformationQuickOverviewASystemCprogramconsistsofmoduledefinitionsplusatop-levelfunctionthatstartsthesimulationModulescontainprocesses(C++methods)heirinterfaceRichsetofportdatatypes(hardwaremodeling,etc.)SignalsinmodulesconveyinformationbetweeninstancesClocksarespecialsignalsthatrunperiodicallyandcantriggerclockedprocessesRichsetofnumerictypes(fixedandarbitraryprecisionnumbers)ModulesHierarchicalentitySimilartoVerilog’smoduleActuallyaC++classdefinitionSimulationinvolvesCreatingobjectsofthisclassTheyconnectthemselvestogetherProcessesintheseobjects(methods)arecalledbytheschedulertoperformthesimulationModulesSC_MODULE(mymod){/*portdefinitions*//*signaldefinitions*//*clockdefinitions*//*storageandstatevariables*//*processdefinitions*/SC_CTOR(mymod){/*Instancesofprocessesandmodules*/}};
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