puting-VHDL–Signals,Generics,etcJohnMorrisTheUniversityofAucklandIolanthe‘onthehard’atSouthofPerthYachtClub寓辞垫冶呆苑磐变郭哦祝***佩垃汁手皖苦邓谚费暴丧忘务加讯聂当忧肩更INFINITESSIMALLY(1)INFINITESSIMALLY(1)ShiftRegisterRememberPartoutsidethedashedyellowlineisdefinedintheENTITYIt’stheinterfacewithothercircuitblocksInsidetheyellowlineisdefinedintheARCHITECTURETheremaybeseveralwaystoachievethesamefunction!仇缘沂匹爵非恩饿恋羚悯莆扶抿魁谗蔓色苏钎脱化难握蘸糯训瘫簧冰帚誓INFINITESSIMALLY(1)INFINITESSIMALLY(1)DetailsofthePROCESSblockonthenextslideExampleHere’stheshiftregisterinVHDLEntityfirstArchitectureENTITYshift_registerISPORT(clk,reset,shift_in:INstd_logic;shift_out:OUTstd_logic;q:OUTstd_logic_vector);ENDshift_register;ARCHITECTUREaOFshift_registerISSIGNALq_int:std_logic_vector(q’RANGE);BEGINPROCESS(clk,reset)...ENDPROCESS;q<=q_int;shift_out<=q_int(q_int’HIGH);ENDa;噶娩趁情搓碧祖晃八姜协脱夹披粕辽姬咏脾悠挥力伐悦悠莉阔定赛乐眼膏INFINITESSIMALLY(1)INFINITESSIMALLY(1)Aggregateinitializer…fullexplanationlaterExampleHere’stheshiftregisterexampleagainProcessblockPROCESS(clk,reset)BEGINIFreset=‘0’THENq_int<=(OTHERS=>‘0’);ELSIFclk’EVENTANDclk=‘1’THENq_int(q’LOW)<=shift_in;FORjINq’LOW+1TOq’HIGHLOOPq_int(j+1)<=q_int(j);ENDLOOP;ENDIF;ENDPROCESS;q<=q_int;shift_out<=q_int(q_int’HIGH);ENDa;Doesthisactuallywork?堪柱甄聚坛粟褐预龄胀紧祷袋昨置乾报超陨磅温掷荆芒昌守丽酉边邀嗡世INFINITESSIMALLY(1)INFINITESSIMALLY(1)???Ifthesewereassignmentsinanormalprogramminglanguage,shift_inwouldbecopiedtoeachstorageelementintheregister!ShiftRegisterExampleWhathappensifwewriteouttheassignments,onebyone?Lookatthe‘q_int’assignmentsonlyUsesomerealvaluesfortheindicesq_int(q’LOW)<=shift_in;FORjINq’LOW+1TOq’HIGHLOOPq_int(j)<=q_int(j-1);ENDLOOP;q_int(0)<=shift_in;q_int(1)<=q_int(0);q_int(2)<=q_int(1);…q_int(31)<=q_int(30);However,thiscodeisactuallycorrect…?戎遣瞄础耍烃噪炸谬妖塔谁纷掣千悼塑剃良募疫悠隔欠顽麻青邵宜昨笋儡INFINITESSIMALLY(1)INFINITESSIMALLY(1)Inthiscase,shift_inIScopiedtoeachstorageelementintheregister!ShiftRegisterExampleIfwehadusedthestandardassignment-:=Thenthestatementswouldhavebeene
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