第一题:普通触发器LIBRARYIEEE;;ENTITYDchuIS PORT(CLK,D:INSTD_LOGIC; Q:OUTSTD_LOGIC); END;ARCHITECTUREFFQOFDchuIS SIGNALQ1:STD_LOGIC;BEGIN PROCESS(CLK,Q1) BEGIN IFCLK'EVENTANDCLK='1' THENQ1<=D; ENDIF; ENDPROCESS; Q<=Q1;ENDFFQ;第二题:异步清零触发器LIBRARYIEEE;;ENTITYDchuIS PORT(CLK,D:INSTD_LOGIC; Q:OUTSTD_LOGIC; ACLK:INSTD_LOGIC); END;ARCHITECTUREFFQOFDchuIS SIGNALQ1:STD_LOGIC;BEGIN PROCESS(ACLK,CLK,Q1) BEGIN IFACLK='1' THENQ1<='0'; ELSIFCLK'EVENTANDCLK='1' THENQ1<=D; ENDIF; ENDPROCESS; Q<=Q1;ENDFFQ;第三题:同步清零触发器LIBRARYIEEE;;ENTITYDchuIS PORT(CLK,D:INSTD_LOGIC; Q:OUTSTD_LOGIC; SCLK:INSTD_LOGIC); END;ARCHITECTUREFFQOFDchuIS SIGNALQ1:STD_LOGIC;BEGIN PROCESS(SCLK,CLK,Q1) BEGIN IFCLK'EVENTANDCLK='1'THEN IFSCLK='1'THEN Q1<='0'; ELSEQ1<=D; ENDIF; ENDIF; ENDPROCESS; Q<=Q1;ENDFFQ;第四题:异步置位apreLIBRARYIEEE;;ENTITYDchuIS PORT( CLK :INSTD_LOGIC; D :INSTD_LOGIC; Q :OUTSTD_LOGIC; APRE :INSTD_LOGIC ); END;ARCHITECTUREFFQOFDchuIS SIGNALQ1:STD_LOGIC;BEGIN PROCESS(APRE,CLK,Q1) BEGIN IFAPRE='1' THENQ1<='1'; ELSIFCLK'EVENTANDCLK='1' THENQ1<=D; ENDIF; ENDPROCESS; Q<=Q1;ENDFFQ;第五题:同步置位spreLIBRARYIEEE;;ENTITYDchuIS PORT( CLK :INSTD_LOGIC; D :INSTD_LOGIC; Q :OUTSTD_LOGIC; SPRE :INSTD_LOGIC ); END;ARCHITECTUREFFQOFDchuIS SIGNALQ1:STD_LOGIC;BEGIN PROCESS(SPRE,CLK,Q1) BEGIN IFCLK'EVENTANDCLK='1'THEN
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