实验四+多路复用器与比较器的设计与仿真.doc

实验四多路复用器与比较器的设计与仿真1、实验目的:实现多路复用器与比较器的设计与仿真。二、,再用VHDL语言设计参数化的多路复用器;,再用VHDL语言设计4位比较器。8-3优先编码器。三、实验步骤。(一)、多路复用器、7485比较器的逻辑图及逻辑表达式。:逻辑框图:逻辑图::逻辑框图:逻辑图:(2)用VHDL语言设计多路复用器、7485比较器。:LIBRARYIEEE; ;ENTITYduoluIS PORT(a:INSTD_LOGIC_VECTOR(1DOWNTO0);c0,c1,c2,c3: INSTD_LOGIC; y :OUTSTD_LOGIC);ENDduolu; ARCHITECTUREarchOFduoluIS BEGIN withAselecty<=c0WHEN"00",c1WHEN"01",c2WHEN"10",c3WHEN"11",  '0'WHENOTHERS;ENDarch;:libraryieee; ;entitybijiaoqiisport(    agbl,albl,aebl:instd_logic;   a0,a1,a2,a3:instd_logic;   b0,b1,b2,b3:instd_logic;    albo,aebo,agbo:outstd_logic);endbijiaoqi; architecturebhvofbijiaoqiisbegin   process(albl,aebl,agbl,a0,a1,a2,a3,b0,b1,b2,b3)   begin      if(a3>b3)then       agbo<='1';albo<='0';aebo<='0';     elseif(a3<b3)then       agbo<='0';albo<='1';aebo<='0';     elseif(a3=b3anda2>b2)then      agbo<='1';albo<='0';aebo<='0';     elseif(a3=b3anda2<b2)then      agbo<='0';albo<='1';aebo<='0';      elseif(a3=b3anda2=b2anda1>b1)then      agbo<='1';albo<='0';aebo<='0';      elseif(a3=b3anda2=b2anda1<b1)then      agbo<='0';albo<='1';aebo<='0';      elseif(a3=b3anda2=b2anda1=b1anda0>b0)then      agbo<='1';albo<='0';aebo<='0';      elseif(a3=b3anda2=b2anda1=b1anda0<b0)then      agbo<='0';albo<='1';aebo<='0';      elseif(a3=b3anda2=b2anda1=b1anda0=b0andaebl='1')th