EDA技术与VHDL -VHDL基础.ppt

EDAEDA技术与技术与VHDLVHDL第3章VHDL VHDL VHDL 组合电路描述图3-1 mux21a实体图3-2 VHDL 组合电路描述【例3-1】ENTITY mux21a IS PORT ( a, b : IN BIT; s : IN BIT; y : OUT BIT );END ENTITY mux21a;ARCHITECTURE one OF mux21a IS BEGIN y <= a WHEN s = '0' ELSE b ;END ARCHITECTURE one ; VHDL 组合电路描述【例3-2】ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux21a;ARCHITECTURE one OF mux21a IS SIGNAL d,e : BIT; BEGINd <= a AND (NOT S) ; e <= b AND s ; y <= d OR e ; END ARCHITECTURE one ; VHDL 基本语法【例3-3】ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT );END ENTITY mux21a;ARCHITECTURE one OF mux21a IS BEGIN PROCESS (a,b,s) BEGIN IF s = '0' THEN y <= a ; ELSE y <= b ;END IF; END PROCESS;END ARCHITECTURE one ; VHDL 基本语法图3-3 VHDL VHDL结构【例3-4】ENTITY e_name IS PORT ( p_name : port_m data_type; ...p_namei : port_mi data_type ); END ENTITY e_name; 1. VHDL 基本语法2. 实体名3. 端口语句和端口信号名4. 端口模式“IN”、“OUT”、“INOUT”、“BUFFER”5. VHDL 基本语法6. 结构体表达【例3-5】ARCHITECTURE arch_name OF e_name IS [说明语句]BEGIN (功能描述语句)END ARCHITECTURE arch_name ; VHDL 基本语法7. 赋值符号和数据比较符号IF a THEN ... -- 注意,a的数据类型必须是boolean IF (s1='0')AND(s2='1')OR(c<b+1) THEN ..8. 逻辑操作符BIT、BOOLEAN、STD_LOGIC AND(与)、OR(或)、NAND(与非)、NOR(或非)、XOR(异或)、XNOR(同或)和NOT(取反)