Lecture10:MemoryHierarchy:ReducingHitTime,MainMemory,&:pulsory,Capacity,-,-blockingCaches(HitunderMiss,MissunderMiss)SecondLevelCacheCanbeappliedrecursivelytoMultilevelCachesDangeristhattimetoDRAMwillgrowwithmultiplelevelsinbetweenFirstattemptsatL2cachescanmakethingsworse,sinceincreasedworstcaseisworseReview:,,-hittime:viaSmallandSimpleCachesWhyAlpha21164has8KBInstructionand8KBdatacache+96KBsecondlevelcache?Smalldatacache(faster)andclockrate(on-chip)DirectMapped,onchipAdvantage:overlaptagcheck&paretakestime.,L1cachessamesizefor3generationsofAMDmicroprocessors:K6,Athlon,andOpteronAlsoL2cachesmallenoughtofitonchipwiththeprocessoravoidstimepenaltyofgoingoffchipSimple-,,-way,4-way,and8-:;otherwisegetfalsehitsCostistimetoflush+“compulsory”missesfromemptycacheDealingwithaliases(sometimescalledsynonyms);TwodifferentvirtualaddressesmaptosamephysicaladdressI/Omustinteractwithcache,soneedvirtualaddressSolutiontoaliasesHWguaranteesthateverycacheblockhasuniquephysicaladdressSWguarantee:lowernbitsmusthavesameaddress;aslo
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