高速自适应判决反馈均衡器地设计.pdf

摘要摘要随着信息时代的快速发展,信息的传输量及传输速率均在日益增大,串行器/解串器(SerDes)便是在这样的背景下逐渐成为了数据传输系统中最常用的结构之一。另一方面, 因自适应判决反馈均衡器能够处理由信道的有限带宽、串扰、阻抗非连续导致的反射等非理想特性所造成的码间干扰,以及信道特性随时间变化等不利因素对传输信号的损害, 其也逐渐成为了SerDes系统的主要模块之一。本文在详细讨论了码间干扰产生的机理并分析了各种均衡器结构的优劣特性之后, 重点阐述了数字域的自适应判决反馈均衡器的设计和实现。本文基于TSMC CMOS工艺,、2抽头的自适应判决反馈均衡器。它主要包括半速率判决反馈均衡电路及系数更新电路。为达到高的工作速率, 判决反馈均衡电路采用了半速率结构,并采用工作速率较高的电流模(Current Model Logic,CML)逻辑设计了其主要的子模块;系数更新电路则主要由误差检测模块、存储抽头系数的上/下计数器及数模转换器3个子模块组成。此外还详细介绍了本系统的偏置电路设计,其由带隙基准参考源及电压转电流模块组成。本文设计的自适应判决反馈均衡器已经流片,并完成了在片测试。测试结果表明, 、,自适应算法在均衡的过程中能起到一定的作用,初步达到了设计要求。在对测试结果进行分析与讨论之后, 本文还给出了自适应算法和电路改进的初步方案和仿真结果,这些都有助于今后高速均衡器的设计和实现。关键词:码间干扰,自适应,判决反馈均衡器,最小均方算法(LMS),电流模逻辑(CML) Absttact Abstract With therapiddevelopment oftheinformation age,the amount and the rate oftheinformation transmission are increasing,and insuch abackground,the SerDes e one monly used structures inthedatatransmission as theadaptive decision feedback equalizer(DFE)is able torestorethedamage tOthe transmission signal which caused bythe non-ideal characteristics ofthe channel,such as thelimitedbandwidth,the crosstalk and the retiection which leaded toby the non-continuous oftheimpedance,as well asthechannel characteristics over limechange andotheradverse factors,it’S ing themain module oftheSerDes. Afterthe detaileddiscussion oftheprinciples ofinter-symbol interference(ISO andtheanalyzed of theprosand COILS ofvariousequalizer structures,thispaper focuses on thedesignand implementation of thedigital domain adaptive decision feedback on theTSMC technology,a 2-tapsadaptive decision feedback equalizer forhigh speed SerDes receiver hasbeendesigned andimplemented,and mainly contains thehalf-ratedecisionfeedbackequalization and the coefficient adaption meet thehigh speedrequirement,the DFE constructed in ahalfrate structure and most ofthesub-modules oftheDFE aredesigned in current mode logic(CML).The COefficientUlXtat