VHDL程序设计题.doc

VHDL程序设计题四、编程题(共50分)1、请补全以下二选一VHDL程序(本题10分)Entitymuxisport(d0,d1,sel:inbit;q:outBIT);(2)endmux;architectureconnectofMUXis(4)signaltmp1,TMP2,tmp3:bit;(6)begincale:blockbegintmp1<=d0andsel;tmp2<=d1and(notsel)tmp3<=tmp1andtmp2;q<=tmp3;(8)endblockcale;endCONNECT;(10)2、编写一个2输入与门的VHDL程序,请写出库、程序包、实体、构造体相关语句,将端口定义为标准逻辑型数据结构(本题10分)LIBRARYIEEE;;(2)ENTITYnand2ISPORT(a,b:INSTD_LOGIC;(4)y:OUTSTD_LOGIC);(6)ENDnand2;ARCHITECTUREnand2_1OFnand2IS(8)BEGINy<=aNANDb;--与y<=NOT(aANDb);等价(10)ENDnand2_1;3、根据下表填写完成一个3-8线译码器的VHDL程序(16分)。LIBRARYIEEE;;ENTITYdecoder_3_to_8ISPORT(a,b,c,g1,g2a,g2b:INSTD_LOGIC;y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));(2)ENDdecoder_3_to_8;ARCHITECTURErtlOFdecoder_3_to_8ISSIGNALindata:STD_LOGIC_VECTOR(2DOWNTO0); (4)BEGINindata<=c&b&a; (6)PROCESS(indata,g1,g2a,g2b)BEGINIF(g1='1'ANDg2a='0'ANDg2b='0')THEN (8)CASEindataISWHEN"000"=>y<="11111110";WHEN"001"=>y<="11111101";WHEN"010"=>y<="11111011"; (10) WHEN"011"=>y<="11110111";WHEN"100"=>y<="11101111";WHEN"101"=>y<="11011111";WHEN"110"=>y<="10111111"; (12) WHEN"111"=>y<="01111111";WHENOTHERS=>y<="XXXXXXXX";ENDCASE;ELSEy<="11111111"; (14)ENDIF;ENDPROCESS; (16)ENDrtl;4、三态门电原理图如右图所示,真值表如左图所示,请完成其VHDL程序构造体部分。(本题14分)LIBRARYIEEE;;ENTITYtri_gateISPORT(din,en:INSTD_LOGIC; dout:OUTSTD_LOGIC);ENDtri_gate;ARCHITECTUREzasOFtri_gateISBEGIN PROCESS(din,en) BEGIN IF(en=‘1')THENdout<=din; ELSE dout<=‘Z’; ENDIF; ENDPROCESS;ENDzas;四、编程题(共50分)1、根据一下四选一程序的结构体部分,完成实体程序部分(本题8分)entityMUX4is port((2) s: instd_logic_vector(1downto0); (4) d: instd_logic_vector(3downto0); (6) y: outstd_logic (8) );endMUX4;architecturebehaveofMUX4isbeginprocess(s) begin if(s="00")then y<=d(0); elsif(s="01")then y<=d(1); elsif(s="10")then y<=d(2); elsif(s="11")then y<=d(3); else null; endif;endprocess;endbehave; 2、编写一个数值比较器VHDL程序的进程(不必写整个结构框架),要求使能信号g低电平时比较器开始工作,输入信号p=q,输出equ为‘0’,否则为‘1’。(本题10分)process(p,q) (2) begin ifg='0'then (4) ifp=qthen equ<='0'; (6) else equ<='1'; (8) endif; else equ<='1'; (1