Designing for Board Level patibility.pdf

? Motorola, Inc., 2002 AN2321/D Rev. 0, 8/2002 Designing for Board Level patibility Application Note By . Lun Applications Engineering Microcontroller Division Hong Kong This application note discusses board level patibility (EMC), ponent selection, circuit design, to printed circuit board layout. The text is divided into the following parts: ? PART 1: An overview of EMC ? PART 2: Component selection and circuit design techniques ? PART 3: Printed circuit board layout techniques ? APPENDIX A: Glossary of EMC terms ? APPENDIX B: Immunity measurement standards PART 1: AN OVERVIEW OF IC INTERFERENCE PATIBILITY ic interference (EMI) is a major problem in modern electronic circuits. To e the interference, the designer has to either remove the source of the interference, or protect the circuit being affected. The ultimate goal is to have the circuit board operating as intended — to achieve patibility (EMC). Achieving board level EMC may not be enough. Although the circuit may be working at the board level, but it may be radiating noise to other parts of the system, causing problems at the system level. Furthermore, EMC at the system or equipment level may have to satisfy certain emission standards, so that the equipment does not affect other equipment or appliances. Many developed countries have strict EMC standards on electrical equipment and appliances; to meet these, the designer will have to think about EMI suppression — starting from the board level. AN2321/D 2 Designing for Board Level patibility MOTOROLA Elements of the ic Environment A simple EMI model consists of three elements: ? EMI source ? Coupling path ? Receptor This is shown graphically in Figure 1 . Figure 1. EMI Elements EMI source EMI sources include microprocessors, microcontrollers, electrostatic discharges, transmitters, transient ponents such as electromechanical relays, switching power supplies, and lightning. Within a microcontroller system, the clock circuitr