数字逻辑设计及应用：chap6 Combinational Logic Design Practices.ppt

Chap6 Combinational logic design practices
Documentation Standards
Design with SSI and MSI blocks
Documentation Standards
Block diagrams
first step in hierarchical design
Schematic diagrams or HDL programs (ABEL, Verilog, VHDL)
Timing diagrams
Circuit descriptions
Example schematic
Which symbol is used?
DeMorgan equivalent symbols
Proper choices of gate symbols can make logic diagrams easier to use and understand
Four AND operations with different active levels
给定逻辑功能只在符号框的内部发生: AND operation
An Inversion Bubble to Indicate an Active-Low,
given logic function as occurring inside that symbol
Signal names are chosen to be descriptive.
Active levels -- HIGH or LOW
TRANSMIT=TRANSMIT_L’
Signal names and active levels
Design with SSI and MSI blocks
Chap6 Combinational logic design practices
Design with SSI and MSI blocks
SSI: Designed with basic logic units
MSI: Designed with functional units
Design with SSI and MSI blocks