Maximizing MLC NAND lifetime and reliability in the ....pdf

Maximizing MLC NAND lifetime and reliability in the presence of write noise Borja Peleato and Rajiv Agarwal Stanford University Email:{peleato, rajivag}***@ Abstract—The aggressive scaling of the NAND ?ash technol- ogy has led to write noise ing the dominant source of disturbance in the currently shipping sub-30 nm MLC NAND memories. Write noise can be mitigated by reducing the mag- nitude of the voltage levels programmed into the cells, which additionally translates to longer ?ash memory lifetime. However, if all the target levels are small and close together, the probability of error could e excessively high. It is therefore necessary to optimize the target level placement in order to achieve a trade-off between ?ash lifetime and error probability. This paper proposes a method to maximize ?ash lifetime subject to reliability constraints, and vice versa. Simulation results show that the proposed method doubles ?ash lifetime parison to a naive scheme, for a 2% reliability constraint. It es very close to the optimal solution obtained by brute force search, while maintaining plexity parison. I. I NTRODUCTION Recently, ?ash memories have emerged as a faster and more ef?cient alternative to hard drives. However, their higher cost is still an obstacle for their widespread use. Manufacturers havesigni?cantly reduced the cost by aggressively scaling the technology and using m