02-Quartus-II时序优化策略.pdf

Quartus II Software Design
Series : Optimization
Optimization Techniques –
Timing Optimization
© 2009 Altera Corporation
1
TimingTiming OptimizationOptimization

General Recommendations

Analyzing Timing Failures

Solving Typical Timing Failures
© 2009 Altera Corporation
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
2
GeneralGeneral RecommendationsRecommendations

Clocks

I/O

Asynchronous Control Signals

Many of these suggestions are found in Timing
Optimization Advisor & Quartus II Handbook
© 2009 Altera Corporation
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
3
ClocksClocks

Optimize for Speed
− Apply globally
− Apply hierarchically
− Apply to specific clock domain

Enable netlist optimizations

Enable physical synthesis
© 2009 Altera Corporation
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
4
GlobalGlobal SpeedSpeed OptimizationOptimization

Select speed
− Default is balanced
− Area-optimized designs may also show speed improvements

May result in increased logic resource usage
© 2009 Altera Corporation
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
5
IndividualIndividual OptimizationOptimization

Optimization Technique logic option
− Use Assignment Editor or Tcl to apply to hierarchical block

Speed Optimization Technique for Clock
Domains logic option
− Use Assignment Editor or Tcl to apply to clock domain or
between clock domains
© 2009 Altera Corporation
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademar