师大学 电气与自动化科学学院 毕业设计(论文) 半导体封装过程wire bond中wire loop的研究及其优化 专 业 机电一体化 班级学号 22010439 学生 晶炎 单位指导教师储焱 学校指导教师 朝晖 评阅教师 2005年5月30日 摘要 在半导体封装过程中,IC芯片与外部电路的连接一段使用金线(-- mils)来完成,金线wire bond过程中可以通过控制不同的参数来形成不同的loop形状,除了金线自身的物理强度特性外,不同的loop形状对外力的抵抗能力有差异,而对于wire bond来说,我们希望有一种或几种loop形状的抵抗外力性能出色,这样,不仅在半导体封装的前道,在半导体封装的后道也能提高mold过后的良品率,即有效地抑制wire sweeping, wire sweeping引起的bond ,我们提出对wire loop的形状进行研究,以期得到一个能够提高wire抗外力能力的途径。 对于wire loop形状的研究,可以解决: 金线neck broken的改善。 BPT数值的升高。 抗mold过程中EMC的冲击力加强。 搬运过程中抗冲击力的加强。 关键词:半导体封装,金线,引线焊接,线型。 Abstract During the process of the semiconductor assembly, we use the Au wire to connect the peripheral circuit from the IC. (The diameter of the Au wire is very small .Usually, it’s about ~2mil.)And during the Au wire bonding, we can get different loop types from control the different parameters. Besides the physics characteristic of the Au wire, the loop types can also affect the repellence under the outside force. For the process of the wire bond, we hope there are some good loop types so that improve the repellence under the outside to this, it can improve the good device ratio after molding. It not only reduces the wire sweeping and the wire open of Au wires but also avoid the bond short cause by the wire sweeping. Therefore, we do the disquisition about the loop type for getting the way to improve the repellence under outside forces. This disquisition can solve the problem about: Improve the neck broken of Au wire. Heighten the BST data. Enhance the resist force to EMC during the molding process. Decrease the possibility of device broken when it be moved. Keyword: the semiconductor assembly, Au wire, wire bond, wire loop. 目录 摘要 ……………………………………………………………………… Abstract………………………………………………………………… 1 绪论…………………………………………………………………… 本课题研究的意义 ………………………………………………