vegas soft vector processor with scratchpad memory拉斯维加斯的软向量处理器暂存存储器.ppt

VEGAS: Soft Vector Processor with Scratchpad Memory
Christopher Han-Yu Chou
Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy Lemieux
University of British Columbia
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Motivation
Embedded processing on FPGAs
High performance, computationally intensive
Soft processors, . Nios/MicroBlaze, too slow
How to deliver High Performance?
Multiprocessor on FPGA
Custom Hardware accelerators (Verilog RTL)
Synthesized accelerators (C to FPGA)
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Motivation
Soft vector processor to the rescue
Previous works have demonstrated soft vector processor as a viable option to provide:
Scalable performance and area
Purely software-based
Decouples hardware/software development
Key performance bottlenecks
Memory access latency
On-chip data storage efficiency
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Contribution
VEGAS Architecture key features
Cacheless Scratchpad Memory
Fracturable ALUs
Concurrent memory access via DMA
Advantages
Eliminates on-chip data replication
Also: huge # of vectors, long vector lengths
More parallel ALUs
Fewer memory loads/stores
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VEGAS Architecture
Scalar Core:
NiosII/f @ 200MHz
DMA Engine & External DDR2
Vector Core:
VEGAS @ 120MHz
Concurrent Execution FIFO synchronized
VEGAS
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Scratchpad Memory in Action
Vector Scratchpad Memory
Vector Lane 0
Vector Lane 1
Vector Lane 2
Vector Lane 3
srcA
srcB
Dest
srcA
srcB
Dest
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Scratchpad Memory in Action
srcA
Dest
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Scratchpad Advantage
Performance
Huge working set (256kB++)
Explicitly managed by software
Async load/store via concurrent DMA
Efficient data storage
Double-clocked memory (Trad. RF 2x copies)
8b data stays as 8b (Trad. RF 4x copies)
No cache (Trad. RF +1 copy)
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Scratchpad Advantage
Accessed by address register
Huge # of vectors in scratchpad
VEGAS uses only 8 vector addr. reg. (V0..V7)
Modify content to access different vectors
Auto-increment lessens need to change V0..V7
Long