【SoCVista】Verification with VCS Workshop.pdf

i-1 Introduction Verification with VCS Workshop Synopsys 37489-000-S11 For BHNEC internal use only. For BHNEC internal use only. Verification with VCS Workshop 37489-000-S11 Synopsys Education and Training Services ?2000 Synopsys, Inc. All Rights Reserved For BHNEC internal use only. i-2 Introduction Verification with VCS Workshop Synopsys 37489-000-S11 For BHNEC internal use only. For BHNEC internal use only. First Things First ? Instructor Introduction ? Student Guide ? Lab Guide i-3 Introduction Verification with VCS Workshop Synopsys 37489-000-S11 For BHNEC internal use only. For BHNEC internal use only. Logistics ? Emergency Exit ? Scheduled Breaks ? Restroom Location ? Placards i-4 Introduction Verification with VCS Workshop Synopsys 37489-000-S11 For BHNEC internal use only. For BHNEC internal use only. Workshop Prerequisites ? Understanding of digital IC design ? Familiarity with UNIX and X-Windows ? Familiarity with a UNIX-based text editor ? Familiarity with Verilog or have attended “Basic Verilog w/VCS” workshop i-5 Introduction Verification with VCS Workshop Synopsys 37489-000-S11 For BHNEC internal use only. For BHNEC internal use only. Workshop Target Audience ? Digital ASIC design engineers ? Digital ASIC verification engineers ? Limited VCS debugging experience i-6 Introduction Verification with VCS Workshop Synopsys 37489-000-S11 For BHNEC internal use only. For BHNEC internal use only. Acquire the skills to verify and debug Verilog designs using Synopsys VCS Workshop Goal i-7 Introduction Verification with VCS Workshop Synopsys 37489-000-S11 For BHNEC internal use only. For BHNEC internal use only. Workshop Measurable Objectives By the end of this workshop you should be able to: ? Simulate Verilog designs using VCS ? Debug Verilog designs using VCS ? Run fast RTL-level regression tests for your Verilog design ? Run fast gate-level regression tests for your Verilog design i-8 Introduction Verification with VCS Workshop Synopsys 37489-000