VHDL电子时钟的设计.docx

扇京师楚大擘
中北学院
现代电子系统设计数字电子钟实验报告
姓
名：
叶子
班
级：
0932班
学
号：
支
业：
电子信息工程
任课教
师：
倪小琦
完成时
间：
2012年5月19日
libraryieee;;;;entity
debounceisport(
clk:instd_logic;
qcin:instd_logic;
qcout:outstd_logic);enddebounce;architecturebehaveofbounceistypestateis(S0,S1,S2);signalcurrent:state;Begin
process(clk,qin)
begin
if(clk'eventandclk='1')thencasecurrentiswhenS0=>qcout<='1';if(qcin='0')thencurrent<=S1;elsecurrent<=S0;endif;whenS1=>qcout<='1';if(qcin='0')thencurrent<=S2;elsecurrent<=S0;endif;whenS2=>qcout<='0';if(qcin='0')thencurrent<=S2;elsecurrent<=S0;endif;whenothers=>qcout<='1';current<=S0;endcase;
endif;
endprocess;endbehave;-2所示:
ilk-：Hz
S=ck1kHz一*
dkdidkHzdkcikiMziielkdklOHs
图3-2分频模块VHD邸言设计如下：
libraryieee;;;;entityclklkHzis
generic(N:integer:=50000);
port
(clk:instd_logic;
clklkHz:outstd_logic
)；endclklkHz;architecturebehaveofclklkHzis
signalcnt:integerrange0toN/2-1;
signaltemp:std_logic;Begin
process(clk)
begin
if(clk'eventandclk='1')thenif(cnt=N/2-1)thencnt<=0;temp<=NOTtemp;elsecnt<=cnt+1;endif;
endif;
endprocess;
clk1KHz<=temp;endbehave;lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllibraryieee;;;;entityclk1Hzis
generic(N:integer:=50000000);
port
(clk:instd_logic;clkIHz:outstd_logic
);endclk1Hz;architecturebehaveofclk1Hzis
signalcnt:integerrange0toN/2-1;
signaltemp:std_logic;Begin
process(clk)
begin
if(clk'eventandclk='1')thenif(cnt=N/2-1)thencnt<=0;temp<=NOTtemp;elsecnt<=cnt+1;endif;
endif;
endprocess;
clk1Hz<=t