fpga可编程逻辑器件芯片ep3c120f484c8n中文规格书.pdf

3. Intel Agilex I/O Termination
UG-20214 |
. OCT Intel FPGA IP Architecture
Figure 40. OCe OCT block
• One output which connects to I/O buffers
Send Feedback3. Intel Agilex I/O Termination
UG-20214 |
Figure 41. OCT Interfaces
RZQ PAD
ser_data
OCT Intel® FPGA IP To I/O Buffers
User Mode OCT
The Fitter does not infer a user-mode OCT. To use the OCT block for user mode
calibration, you must generate the OCT IP. The IP uses the calibration_request
and ack_recal signals to send and receive calibration request from the core.
The core initiates a calibration request to the OCT IP by asserting the
calibration_request signal to high for at least 2 µs. The OCT IP asserts the
ack_recal signal to the core to indicate that the IP has received the request.
You can only use the OCT IP in user mode with the GPIO IP. Connect the
terminationcontrol signal from the GPIO IP to the ser_data signal in the OCT IP
using R