fpga可编程逻辑器件芯片ep3c40f324i8n中文规格书.pdf

Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLL_<L1/L4/R1/R4>_CLK (1)
GCLK/RCLK (2) inclk0
4
CLK[0..3] or CLK[8..11] (3)
inclk1
4
Notes to Figure 6–12:
(1) Dedicated clock input pins to PLLs - L1, L4, R1 and R4, respectively. For example, PLL_L1_CLK is the dedicated
clock input for PLL_L1.
(2) The global (GCLK) or regional (RCLK) clock input can be driven by an output from another PLL, a pin-driven global
or regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin driven dedicated global or regional clock. An internally generated global signal or general purpose I/O
pin cannot drive the PLL.