fpga可编程逻辑器件芯片ep3sl70f780c2中文规格书.pdf

5. Native Fixed Point DSP Intel Agilex FPGA IP Core References
UG-20213 |
Signal Name information about clock enable restrictions for input registers.
Table 73. Dynamic Control Signals
For summary of supported dynamic control features for each operational modes, please refer to Table 2 on
page 7
Signal Name Type Width Description
disable_chainout Input 1 Dynamic input signal to enable dynamic chainout feature. You can change the value
of this signal during run-time.
You must connect the chainout output bus to the next DSP block in order to use
this signal.
• 0: Send the chainout output to the next DSP block. Default value.
• 1: Do not send the chainout output to the next DSP block. The chainout
output is all zero.