Quartus II软件使用教程.ppt

Quartus_II软件使用教程Quartus II 软件使用教程
Vincent Song
Q2 2008
Cytech-XA
Structured ASIC
HardCopy® II & HardCopy Stratix
High & medium density FPGAs
Stratix III, Stratix II & Stratix
Low-cost FPGAs
Cyclone III, Cyclone II & Cyclone
FPGAs w/ clock data recovery
Stratix II GX & Stratix
Low-cost 90-nm FPGAs for PCI Express, Gigabit ,and Serial RapidIO up to Gbps
Arria GX
CPLDs
MAX II, MAX 7000 & MAX 3000
Configuration devices
Serial (EPCS) & enhanced (EPC)
Programmable Logic Families
2
QuartusII软件发布RoadMap
Q4
Q1
Q2
Q3
Q4
2006

Windows 2000
Windows XP (32-bit & 64-bit)
Red Hat Enterprise 3 (32 / 64 -bit)
Linux
Sun
Windows
Q1

Q2
2007
Q3
Q4
Q1
2008
Red Hat Enterprise 4 (32 / 64-bit)
Suse Server 9 (32 / 64-bit)





Solaris 8 / 9 (32-bit & 63-bit)
2009
Red Hat Enterprise 5
New
Windows Vista
3
Multi-processor cores now mainstream
Benefit  pile times
64-Bit O/S – moving mainstream
Benefit  access to more than 2 GB of memory
从QII
4
Quartus II开发环境
资源管理窗
信息显示窗
编辑状态显示窗
工程工作区
工具栏
5
主要快捷键
Compilation report
Chip Planner
(Floorplan & Chip Editor)
Execution controls
Assignment
Editor
Settings
Pin Planner
Programmer
To open step by pilation flow:
Tools  Customize  Toolbars
Select “Processing” Check Box
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Agenda
设计流程概要
建立工程
设计输入
编译
综合
使用Synplify Pro做综合
布局布线
Assignment Editor
管脚分配
仿真
器件编程
时序约束
SignalTap II 逻辑分析仪
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Quartus II 软件使用教程
设计流程概要
Typical PLD Design Flow
Synthesis
- Translate design into device specific primitives
- Optimization to meet required area & performance constraints
- Quartus II, Precision Synthesis, Synplify/Synplify Pro,
piler FPGA
Design Specification
Place & route
- Map primitives to specific locations inside
Target technology with reference to area &
performance constraints
- Specify routing resources to be used
Design entry/RTL coding
- Behavioral or structural description of design
RTL simulation
- Functional simulation (ModelSim®, Quartus II)
- Ve