国际学术会议海报模板20-academic conference poster model.ppt

Best case 3D (Arch 3/WI) performs 12% better than best case 2D (Replicated Cache banks).
Better thermal profile : Best case (Arch 3/ WI) has just 10 0 C increase from 2D with maximum performance gains
Understanding the Impacts of 3D Stacked Layouts on ILP
Vivek Venkatesan, Manu Awasthi, Rajeev Balasubramonian
School puting, University of Utah
Interconnects within a processor pipeline are known to be a major bottleneck for performance and power in future processors. Wire delays are Vertical 3D stacking of dies allows reduction of overall wire-lengths and helps alleviate the performance and power overhead of on-chip wiring. The primary disadvantage is that it results in increased power-densities and on-chip temperatures.
Floor-planning generates arbitrary layouts of micro-architectural
blocks in a processor evaluating each with respect to an
objective function
Include delay-criticality information in the objective function to
keep municating blocks closer
3D floor-planning generates 3D layouts, more potential to exploit
closeness in the vertical dimension
Wire-latencies predicted to be in 10’s of cycles in future fabrication technologies
Studying the impact of wire-delays on performance reinforces the need for interconnect optimization techniques
Popular belief: Multi-threading hides wire-delays, not entirely true!
Technique to alleviate key wire-delays -> Floo