miao_60的源代码: library ieee; use ; use ; use ; entity miao_60 is port(clk :in std_logic; --输入1HZ的频率 rst :in std_logic; --rst 复位 shi: out std_logic_vector(3 downto 0); --秒的十位、个位 ge: out std_logic_vector(3 downto 0); carry :out std_logic ); --满59s进位给分钟作频率 end entity miao_60; architecture art1 of miao_60 is signal tem1: std_logic_vector(3 downto 0); --定义与端口等宽的信号 signal tem2: std_logic_vector(3 downto 0); --位矢量 begin process(clk,rst) begin if(rst='0' ) then tem1<="0000"; --复位时十、个位归零 tem2<="0000"; elsif clk'event and clk='1' then if tem1="1001" then --个位计到9时归零 tem1<="0000"; if tem2="0101" then --十位到5时归零 tem2<="0000"; carry<='1'; --给分钟进位作为分钟的时钟频率 else tem2<=tem2+1; carry<='0'; end if; else tem1<=tem1+1; end if; end if; shi<=tem2;ge<=tem1; end process; end a