chapter04 The Wire_ex.pdf

1 Chapter 4 Problem Set
Chapter 4
Problems
1. [M, None, ] Figure shows a clock-work. Each segment of the -
work (between the nodes) is 5 mm long, 3 µm wide, and is implemented in polysilicon. At
each of the terminal nodes (such as R) resides a load capacitance of 100 fF.
a. Determine the average current of the clock driver, given a voltage swing on the clock lines
of 5 V and a maximum delay of 5 nsec between clock source and destination node R. For
this part, you may ignore the resistance and inductance of work
b. Unfortunately the resistance of the polysilicon cannot be ignored. Assume that each
straight segment of work can be modeled as a work. Draw the equivalent cir-
cuit and annotate the values of resistors and capacitors.
c. Determine the dominant time-constant of the clock response at node R.
S
Figure Clock-work.
R
2. [C, SPICE, ] You are designing a clock work in which it is critical to mini-
mize skew between local clocks (CLK1, CLK2, and CLK3). You have extracted the -
work of Figure , which models the routing parasitics of your clock line. Initially, you
notice that the path to CLK3 is shorter than to CLK1 or CLK2. In order pensate for this
imbalance, you insert a transmission gate in the path of CLK3 to eliminate the skew.
a. Write expressions for the time-constants associated with nodes CLK1, CLK2 and CLK3.