verilogHDL交通灯设计.docx

交通灯设计第一模块分频模块把50MHz分成1Hzmoduledivider(clk_50MHz,clk_1Hz);inputclk_50MHz;outputclk_1Hz;regclk_1Hz;reg[30:0]count;parameterN=50000000;always@(posedgeclk_50MHz)beginif(count==N/2-1)beginclk_1Hz<=clk_1Hz+1'b1;count<=0;endelsecount<=count+1'b1;endendmodule第二模块60进制计数器程序:modulecounter60(clkin,reset,countnum);inputclkin,reset;//reset复位output[5:0]countnum;reg[5:0]countnum;always@(posedgeclkin)beginif(!reset)countnum<=0;elsebeginif(countnum==59)//六十进制计数countnum<=0;elsecountnum<=countnum+1;endendendmodule第三模块控制器程序:modulecontrol(clk,countin,start_sn,start_ew,redn,reds,rede,redw,greenn,greens,greene,greenw);inputclk;input[5:0]countin;//60进制计数器outputstart_sn,start_ew;//控制东西、南北方向倒计时控制开关outputredn,reds,rede,redw;//东西南北红灯开关outputgreenn,greens,greene,greenw;//东西南北绿灯开关regstart_sn,start_ew;regredn,reds,rede,redw;reggreenn,greens,greene,greenw;always@(posedgeclk)beginif(countin==0)beginstart_sn<=1;start_ew<=0;endelseif(countin>=1&&countin<=24)beginstart_sn<=0;start_ew<=0;greenn<=0;greens<=0;greene<=1;greenw<=1;redn<=1;reds<=1;rede<=0;redw<=0;endelseif(countin>24&&countin<30)beginstart_sn<=0;start_ew<=0;greenn<=0;greens<=0;greene<=0;greenw<=0;redn<=1;reds<=1;rede<=1;redw<=1;endelseif(countin==30)beginstart_sn<=0;start_ew<=1;endelseif(countin>30&&countin<=59)beginstart_sn<=0;start_ew<=0;greenn<=1;greens<=1;greene<=0;greenw<=0;redn<=0;reds<=0;rede<=1;redw<=1;endendendmodule第四模块位倒计时控制程序:moduleanticount(clk_1Hz,start,data1,data10,enable);inputclk_1Hz,start;outputenable;output[3:0]data10,data1;//倒计时计数regenable;reg[3:0]data10,data1;reg[4:0]count;always@(posedgestartornegedgeclk_1Hz)beginif(start)enable<=1'b1;elseif(count==0)enable<=1'b0;endalways@(posedgeclk_1Hz)beginif(enable)beginif(count==0)count<=5'b11110;elsecount<=count-1'b1;endelsecount<=5'b00000;endalways@(negedgeclk_1Hz)beginif(enable)begindata10<=count/10;data1<=count%10;endelsebegindata10<=4'b0000;data1<=4'b0000;endendendmodule第五模块显示电路程序moduledisplay(clk,enable,datain,discode);inputclk,enable;input[3:0]datain;output[6:0]discode;reg[