时钟分频.doc

EDA实验报告山农大电子实验名称时钟分频实验目的学****数控分频器的设计、分析和测试方法。实验原理数控分频器的功能就是当在输入端给定不同输入数据时,将对输入的时钟信号有不同的分频比,数控分频器就是用计数值可并行预置的加法计数器设计完成的,方法是将计数溢出位与预置数加载输入信号相接即可。实验要求将clock5连接至4096Hz,编写分频逻辑,将其分频至1Hz,2Hz,8Hz,16Hz,编写四选一MUX,可用按键控制选择分频后的某时钟。扩展实验3中的计数器,使其能计数0-99,并编写顶层文件例化分频逻辑、选择器、计数器,使计数器在不同的频率下计数。实验步骤【1】分频逻辑:libraryieee;;;entitydvfisport(clk:instd_logic; s:instd_logic_vector(1downto0);clkend:outstd_logic);end;architectureoneofdvfissignalclk1_tmp:std_logic;signalclk2_tmp:std_logic;signalclk3_tmp:std_logic;signalclk4_tmp:std_logic;t2048:integerrange0to2048;t1024:integerrange0to1024;t512:integerrange0to512;t256:integerrange0to256;beginfen1:process(clk)beginifclk'eventandclk='1'then t2048<t2048<=cnt2048+1; t2048<=0; clk1_tmp<=NOTclk1_tmp; endif; endif;endprocess;fen2:process(clk)beginifclk'eventandclk='1'then t1024<t1024<=cnt1024+1; t1024<=0; clk2_tmp<=NOTclk2_tmp; endif; endif;endprocess;fen8:process(clk)beginifclk'eventandclk='1'then t512<t512<=cnt512+1; t512<=0; clk3_tmp<=NOTclk3_tmp; endif; endif;endprocess;fen16:process(clk)beginifclk'eventandclk='1'then t256<t256<=cnt256+1; t256<=0; clk4_tmp<=NOTclk4_tmp; endif; endif;endprocess;xz:process(s) begin casesis when"00"=>clkend<=clk1_tmp; when"01"=>clkend<=clk2_tmp; when"10"=>clkend<=clk3_tmp; when"11"=>clkend<=clk4_tmp; whenothers=>null; endcase; endprocess;【2】计数器libraryieee;