verilog 有限状态机设计.ppt

、(Moore)状态机米里型(Mealy)(clk,clr,z,qout);//模5计数器inputclk,clr;outputregz;outputreg[2:0]qout;always@(posedgeclkorposedgeclr) //此过程定义状态转换begin if(clr)qout<=0; //异步复位 elsecase(qout) 3'b000:qout<=3'b001; 3'b001:qout<=3'b010; 3'b010:qout<=3'b011; 3'b011:qout<=3'b100; 3'b100:qout<=3'b000; default:qout<=3'b000; /*default语句*/ endcaseendalways@(qout) /*此过程产生输出逻辑*/begincase(qout) 3'b100:z=1'b1; default:z=1'b0;=0State0out=001clr=1step3=0State2out=100State1out=010start=1step3=1State3out=111step2=1step2=0.【】状态机设计举例moduleFSM(clk,clr,out,start,step2,step3);inputclk,clr,start,step2,step3;output[2:0]out;reg[2:0]out;reg[1:0]state,next_state;parameterstate0=2’b00,state1=2’b01,//状态编码 state2=2’b11,state3=2’b10;//格雷码always@(posedgeclkorposedgeclr)begin if(clr) state<=state0;//定义初态 else state<=next_state;@(stateorstartorstep2orstep3)//状态转换begincase(state) state0: begin if(start)next_state<=state1; else next_state<=state0; end state1: begin next_state<=state2; : begin if(step2)next_state<=state3; else next_state<=state0; end state3: begin if(step3)next_state<=state0; else next_state<=state3; end default: next_state<=state0;endcaseend.