OrCAD Capture User Guide -- 4. Working with designs.pdf

OrCADCaptureUserGuide, ProductVersion 4 Working withdesigns Thischaptercovers: Creatinganewdesign Creatinganewschematicpage Creatinganewtextfile CreatinganewVHDLorVerilogfile Captureprovidesthemeanstocreateelectronicdesignsintwomedia:asschematicsor as VHDLmodels. SchematicdesignscanincludeVHDLorVerilogmodels(oneortheother, notboth)as lowerlevelhierarchicalmodules, butthesemodelscanonlyinstantiateothermodels(of thesametype)atlowerlevelsinthehierarchy. Considerthefollowingillustration: AnyschematicdesignmodulecanincludeeitherschematicsorVHDL/Verilogmodelsas ponents. However, VHDL/Verilogdesignmodulesarelimitedtoother ponents. Hence, iftherootmoduleofyour designisaVHDLmodel, alllowerlevelmodulesmustalsobeVHDLmodels. Note: Ifyouhaven'tspecifiedarootforyourdesign, youcannotgeneratereports. Also, 1 whenfoldersarecopiedtoanewdesign, theROOTdesignationislostandmustbe reestablishedinthedesign. Creatinganewdesign Thissectioncovers: Creatinganewdesignfilebeforepopulatingtheproject Creatinganewdesignaftertheprojectispopulated Note: Therecanbeonlyonedesignfileinaproject. Ifyoucreateanewdesignfile, or moveorcopyadifferentoneintotheproject, theprojectmanagerwillaskyouifyou wanttoreplacetheexistingdesignfile. Creating a newdesign filebeforepopulating theproject Whentheprojectisfirstcreated, theprojectmanagercreatesadesignfilewiththesame nameastheproject. Italsocreatesasc