60-Ghz Cmos Phase-Locked Loops - H Cheema, Et Al , (Springer, 2010) Ww.pdf

60-GHz CMOS Phase-Locked Loops
Hammad M. Cheema l Reza Mahmoudi l
Arthur H. M. van Roermund
60-GHz CMOS
Phase-Locked Loops
Hammad M. Cheema Reza Mahmoudi
Eindhoven University of Eindhoven University of
Technology Technology
Electrical Engineering Electrical Engineering
Den Dolech 2 Den Dolech 2
5600 MB Eindhoven 5600 MB Eindhoven
herlands
.******@ r.******@
Dr. Arthur H. M. van Roermund
Eindhoven University of
Technology
Dept. Electrical Engineering
Eindhoven
Netherlands
.******@
ISBN 978-90-481-9279-3 e-ISBN 978-90-481-9280-9
DOI -90-481-9280-9
Springer Dordrecht Heidelberg London New York
Library of Congress Control Number: 2010930220
# Springer ScienceþBusiness Media . 2010
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Contents
1 Introduction ................................................................ 1
2 Synthesizer System Architecture ......................................... 11
IEEE Channelization ....................................... 13
60 GHz Frequency Conversion Techniques ........................... 14
Proposed PLL Architecture: Flexible, Reusable,
Multi-frequency ........................................................ 17
Utilization in m Project ................................ 18
System Analysis and Design .......................................... 18
Phase-Lock Loop Basics ........................................ 19
Frequency Planning ........