dxp原理图常见错误.doc

原理图常见错误principle of common mistakes
1、ERC报告管脚没有接入信号ERC report no access to signal pins
1）创建封装时给管脚定义了I/O属性creation package to the pin at the definition of I/O attribute
2）创建元件或放置元件时修改了不一致的grid属性，管脚与线没有连上。create components or modify components placed inconsistent grid attributes, and the lines do not pin connection;
3）创建元件时pin方向反向，必须非pin name端连线。create components reverse direction when the pin, non-name-pin connections.
2、元件跑到图纸界外：没有在元件库图表纸中心创建元件。 components went to the drawings profession : no paper charts component library center components.
3、创建的工程文件网络表只能部分调入pcb：生成netlist时没有选择为global。the creation of the document network table works only partially transferred PCB : netlist generation did not choose to global.
4、当使用自己创建的多部分组成的元件时，千万不要使用annotate. When the use of their own creation, multi-component element, we must use annotate.
PROTEL DXP2004 DRC 中英文对照
一、Error Reporting 错误报告
1、Violations Associated with Buses 总线电气错误（共12项）
1）bus indices out of range 总线分支索引超出范围
2）Bus range syntax errors 总线范围的语法错误
3）Illegal bus range values 非法的总线范围值
4） Illegal bus definitions 定义的总线非法
5）Mismatched bus label ordering 总线分支网络标号错误排序
6）Mismatched bus/wire object on wire/bus 总线/导线错误的连接导线/总线
7）Mismatched bus widths 总线宽度错误
8）Mismatched bus section index ordering 总线范围值表达错误
9）Mismatched electrical types on bus 总线上错误的电气类型
10）Mismatched generics on bus (first index) 总线范围值的首位错误