fpga可编程逻辑器件芯片ep2sgx60ef1152c45中文规格书.pdf

Stratix II Architecture
Fast PLLs
Stratix II devices contain u ÷c3
÷m
8
to DPA block
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–45:
(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. Stratix II
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(3) This signal is a differential I/O SERDES control signal.
(4) Stratix II fast PLLs only support manual clock switchover.
(5) If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
f See the PLLs in Stratix II & Stratix II GX Devic