52 A low-noise fast-lock phase-locked loop with adaptive bandwidth control.pdf

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 1137
A Low-Noise Fast-Lock Phase-Locked Loop with
Adaptive Bandwidth Control
Joonsuk Lee, Student Member, IEEE, and Beomsup Kim, Senior Member, IEEE
Abstract—This paper presents a salient analog phase-locked respond properly to unpredictable phase fluctuation, instant
loop (PLL) that adaptively controls the loop bandwidth according frequency shift, and time-varying jitter because the sequence
to the locking status and the phase error amount. When the phase was calculated with preknown fixed noise statistics.
error is large, such as in the locking mode, the PLL increases the
loop bandwidth and achieves fast locking. On the other hand, Discrete-time PLL’s, which are programmed on DSP proces-
when the phase error is small, this PLL decreases the loop band- sors, based on a recursive least squared (RLS) algorithm [5]
width and minimizes output jitters. Based on an analog recursive or the Kalman filter algorithm [6] can respond to such unpre-
bandwidth control algorithm, the PLL achieves the phase and dictable jitter variations, but require enormous amount of hard-
frequency lock in less than 30 clock cycles without pre-training, ware. The outputs generated from the discrete-time PLL’s are
and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak)
in the tracking mode. A feed forward-type du