3,4,5分频电路设计并仿真.docx

1,使用原理图文件设计三分频电路:
仿真需要设置function功能,然后生成网表(processing)
仿真结果:
2,使用Verilog 程序设计三分频,四分频,五分频设计
三分频:
module sanfp(clkin,clkout);
input clkin;
output clkout;
reg[1:0] step1,step;
always @(posedge clkin)
begin
case (step)
2'b00:step<=2'b01;
2'b01:step<=2'b10;
2'b10:step<=2'b00;
default:step<=2'b00;
endcase
end
always @(negedge clkin)
begin
case(step1)
2'b00:step1<=2'b01;
2'b01:step1<=2'b10;
2'b10:step1<=2'b00;
default:step1<=2'b00;
endcase
end
assign clkout=~(step1[1]|step[1]);
endmodule
四分频:
module sifenp(clkin, clkout);
input clkin;
output clkout;
reg[1:0] count1;
always @(posedge clkin)
begin
case (count1)
2'b00: count1<=2'b01;
2'b01: count1<=2'b10;
2'b10: count1<=2'b11;
2'b11: count1<=2'b00;
default count1<=2'b00;
endcase
end
assign clkout=count1[1];
endmodule
五分频:
module fivefp(clkin, clkout,clkout1,clkout2);
input clkin;
output clkout,clkout1,clkout2;
reg[2:0] cnt1, cnt2;
always @(posedge clkin)
begin
case (cnt1)
3't1<=3'b001;