VHDL语言设计数字秒表.doc

四、VHDL源程序时基分频模块的VHDL源程序()LIBRARYIEEE;;;ENTITYCB10ISPORT(CLK:INSTD_LOGIC;--输入时钟信号CO:OUTSTD_LOGIC);--分频输出信号ENDCB10;ARCHITECTUREARTOFCB10ISSIGNALCOUNT:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIFRISING_EDGE(CLK)THENIFCOUNT="1001"THENCOUNT<="0000";CO<='1';ELSECOUNT<=COUNT+1;CO<='0';ENDIF;ENDIF;ENDPROCESS;ENDART;2、控制模块的VHDL源程序()LIBRARYIEEE;;;ENTITYCTRLISPORT(CLR,CLK,SP:INSTD_LOGIC;EN:OUTSTD_LOGIC);END;ARCHITECTUREBEHAVEOFCTRLISCONSTANTS0:STD_LOGIC_VECTOR(1DOWNTO0):="00";CONSTANTS1:STD_LOGIC_VECTOR(1DOWNTO0):="01";CONSTANTS2:STD_LOGIC_VECTOR(1DOWNTO0):="11";CONSTANTS3:STD_LOGIC_VECTOR(1DOWNTO0):="10";TYPESTATESIS(S0,S1,S2,S3);SIGNALCURRENT_STATE,NEXT_STATE:STATES;:PROCESS(SP,CURRENT_STATE)BEGINCASECURRENT_STATEISWHENS0=>EN<='0';IFSP='1'THENNEXT_STATE<=S1;ELSENEXT_STATE<=S0;ENDIF;WHENS1=>EN<='1';IFSP='1'THENNEXT_STATE<=S1;ELSENEXT_STATE<=S2;ENDIF;WHENS2=>EN<='1';IFSP='1'THENNEXT_STATE<=S3;ELSENEXT_STATE<=S2;ENDIF;WHENS3=>EN<='0';IFSP='1'THENNEXT_STATE<=S3;ELSENEXT_STATE<=S0;ENDIF;ENDCASE;ENDPROCESS;SYNCH:PROCESS(CLK)BEGINIFCLR='1'THENCURRENT_STATE<=S0;ELSIFCLK'EVENTANDCLK='1'THENCURRENT_STATE<=NEXT_STATE;ENDIF;ENDPROCESS;ENDBEHAVE;3、计时模块的VHDL源程序(1)十进制计数器的VHDL源程序()LIBRARYIEEE;;;ENTITYCDU10ISPORT(CLK:INSTD_LOGIC;--时钟信号CLR:INSTD_LOGIC;--清零信号EN:INSTD_LOGIC;--:OUTSTD_LOGIC;--记数输出信号 COUNT10:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCDU10;ARCHITECTUREARTOFCDU10ISSIGNALSCOUNT10:STD_LOGIC_VECTOR(3DOWNTO0);BEGINCOUNT10<=SCOUNT10;PROCESS(CLK,CLR,EN)BEGINIF(CLR='1')THENSCOUNT10<="0000";CN<='0';ELSIFRISING_EDGE(CLK)THENIF(EN='1')THENIFSCOUNT10="1001"<='1';SCOUNT10<="0000";<='0';SCOUNT10<=SCOUNT10+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;ENDART;(2)六进制计数器的VHDL源程序()LIBRARYIEEE;;;ENTITYCDU6ISPORT(CLK,CLR,EN:INSTD_LOGIC;--:OUTSTD_LOGIC;--计数输出信号COU