IGZO-电路版图总结
胡治晋
2016. 01. 22
主 要 内 容
一、工艺流程
二、 设计规则
三、单元模块
四、版图布局
五、后续工作
六、近期GOA文献
一、工艺流程
两套BCE工艺流程
有源层做好后,先开栅孔,淀积S/D完成互联;
最少需要5块版, ITO淀积可不做。
最后采用ITO互联;
最少需要6块版。
兼容流程1/流程2
通孔大小:6um 6um
10u
2u
2u
6
L_ESL=10u L_BCE=6u
SD与ESL层之间交叠:2u;
ESL层最小宽度:2+2+6=10u
ESL层之间的间距:4u;
SD最小宽度(叉指宽度):2+2+4=8u
TFT器件
接触孔单元(Via)
流程1
流程2
二、设计规则(1)
由M1引出的I/O PAD
由M2引出的I/O PAD
电路中I/O PAD排布方式
I/O PAD
二、设计规则(2)
三、单元模块(1)
GOA
PIXEL CIRCUIT
INV, Ring Oscallator
对准模块Align & TFT
Layout中的各单元模块示意图
器件版中的TFT阵列
Align &TFT阵列
对准符号与旧器件版相同,便于流片。
对准模块中包括旧器件版中常用TFT阵列。
TFT模块中截取旧器件版中常用TFT阵列。
对准模块:Align & TFT
三、单元模块(2)
对准模块:TFT & Align
TFT模块
旧器件版中的阵列单元
共需7块版: Gate, Active,ESL, ViaG, S/D,ViaSD,ITO。
模块区包括:GOA, Pixel, INV, Oscillator, Align & TFT(旧版复制)
布局优化,可同时采用2寸或4寸玻璃片流片;
四、版图布局
绿块为对准模块
或TFT阵列区
汇总Layout各电路模块的技术文档;
检查Layout设计规则,电学连接;
光刻版制造
搭建外部测试平台;
五、后续工作
六、GOA文献1-1
1. Guan-Ming Li, “Design of high speed gate driver employing IZO TFTs” South China University of Technology, Displays, 12月, 2015.
The metal oxide thin film transistors (MO TFTs) such as zinc-oxide (ZnO) TFTs [5,6], indium-gallium-zinc-oxide (IGZO) TFTs [7,8], and indium-zincoxide (IZO) TFTs [9,10] have gained much interest as a promising technology for the next generation of FPD due to the high mobility, low sub-threshold voltage swing, high current on/off ratio, and good process compatibility with a-Si TFTs.
There are some difficulties for MO TFTs to integrate the gate driver because they operate in a depletion mode with threshold voltage around zero compared with a-Si:H TFTs or LTPS TFTs.
In addition, the high speed gate driver is urgently required for the display with high resolution such as 4096 2160 or high frame rate such as 240 Hz.
Three important factors needs to be taken into account: schematic of gate driver, the optimized timing and the optimization for the sizes of devices.
提出了一种采用IZO-TFT的高速GOA,适用于高帧频、高分辨率显示器
igzo-电路版图总结(ppt课件) 来自淘豆网www.taodocs.com转载请标明出处.