Document serial number【UU89WT-UU98YT-UU8CB-UUUT-UUT108】
VHDL各种D触发器程序
第一题:普通触发器
LIBRARY IEEE;
USE Dchu IS
PORT (CLK,D:IN STD_LOGIC;
Q:OUT STD_LOGIC);
END;
ARCHITECTURE FFQ OF Dchu IS
SIGNAL Q1:STD_LOGIC;
BEGIN
PROCESS (CLK,Q1)
BEGIN
IF CLK'EVENT AND CLK='1'
THEN Q1<=D;
END IF;
END PROCESS;
Q<=Q1;
END FFQ;
第二题:异步清零触发器
LIBRARY IEEE;
USE Dchu IS
PORT (CLK,D:IN STD_LOGIC;
Q:OUT STD_LOGIC;
ACLK:IN STD_LOGIC);
END;
ARCHITECTURE FFQ OF Dchu IS
SIGNAL Q1:STD_LOGIC;
BEGIN
PROCESS (ACLK,CLK,Q1)
BEGIN
IF ACLK='1'
THEN Q1<='0';
ELSIF CLK'EVENT AND CLK='1'
THEN Q1<=D;
END IF;
END PROCESS;
Q<=Q1;
END FFQ;
第三题:同步清零触发器
LIBRARY IEEE;
USE Dchu IS
PORT (CLK,D:IN STD_LOGIC;
Q:OUT STD_LOGIC;
SCLK:IN STD_LOGIC);
END;
ARCHITECTURE FFQ OF Dchu IS
SIGNAL Q1:STD_LOGIC;
BEGIN
PROCESS (SCLK,CLK,Q1)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF SCLK='1' THEN
Q1<='0';
ELSE Q1<=D;
END IF;
END IF;
END PROCESS;
Q<=Q1;
END FFQ;
第四题:异步置位apre
LIBRARY IEEE;
USE Dchu IS
PORT (
CLK : IN STD_LOGIC;
D : IN STD_LOGIC;
Q :OUT STD_LOGIC;
APRE :IN STD_LOGIC
);
END;
ARCHITECTURE FFQ OF Dchu IS
SIGNAL Q1:STD_LOGIC;
BEGIN
PROCESS (APRE,CLK,Q1)
BEGIN
IF APRE='1'
THEN Q1<='1';
ELSIF CLK'EVENT AND CLK='1'
THEN Q1<=D;
END IF;
END PROCESS;
Q<=Q1;
END FFQ;
第五题:同步置位spre
LIBRARY IEEE;
USE Dchu IS
PORT (
CLK : IN STD_LOGIC;
D : IN STD_LOGIC;
Q :OUT STD_LOGIC;
SPRE :IN STD_LOGIC
);
END;
ARCHITECTURE FFQ OF Dchu IS
SIGNAL Q1:STD_LOGIC;
BEGIN
PROCESS (SPRE,CLK,Q1)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF SPRE='1' THEN
Q1<='1';
ELSE Q1<=D;
END IF;
END IF;
END PROCESS;
Q<=Q1;
END FFQ;
第六题:异步清零,异步置位
LIBRARY IEEE;
USE Dchu IS
PORT (
CLK : IN STD_LOGIC;
ACLR : IN STD_LOGIC;
APRE
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